SAND 97 - 1721 UC - 704 Unlimited Release Printed July 1997 High Reliability Plastic Packaging for Microelectronics

This Laboratory Directed Research & Development (EDRD) project conducted in fiscal years 1996 and 1997 under case 3526.030 was devoted to the development of test structures and associated measurement methodology for assessing the reliability of plastic encapsulated microelectronic devices. The end goal was the conceptual specification of one or more Assembly Test Chips (ATCs) which could be used evaluating plastic encapsulation technologies. In the course of this work we demonstated suitable circuits for measuring Au-A1 wirebond and A1 metal corrosion failure rates during accelerated temperature and humidity testing. We also showed that the test circuits on our ATC02.5 chip were very sensitive to extrinsic or processing induced failure rates. A number of accelerated aging experiments were conducted with unpassivated triple track A1 structures on the ATC02.6 chip to demonstrate that these would be extremely sensitive to environmental conditions. We found an unexpected result, the unpassivated tracks were very sensitive to particulate contamination which caused conductor damage and resultant high voltage breakdown. A number of modifications to existing circuitry were suggested as a result of the unpassivated device experiments. We also showed that the piezoresistive stress sensing circuitry whch we had designed for the ATCO4 test chip was suitable for determining the change in the state of mechanical stress at the die when both initial and final measurements were made near room temperature. However, our attempt to measure thermal stress between room temperature and a typical polymer glass transition temperature failed because of excessive die resistorsubstrate leakage currents at the high temperature end. Suitable circuitry changes were developed which should eliminate this problem. One temperature and humidity experiment was conducted with Sandia developed static random access memory (SRAM) parts to examine non-corrosion CMOS failures. This experiment did not achieve the desired objective because of processing problems but we did demonstrate that we could easily detect and measure a new type of corrosion failure mode, this time at the metal to Si contacts on the die surface. As a result of this two year effort, we have new designs for a number of test circuits which could be used on an advanced ATC for reliability assessment in Defense Programs electronics development projects.